Identification and Modeling the Shared

My research in computer architecture area mainly focuses on supporting Quality of Service in Chip MultiProcessors and analytically modeling the performance of cache/memory systems. The scaling, power, thermal and reliability constraints of the uniprocessors have turned the focus of the computer industry towards chip muti-processor (CMP) systems in many computing domains. Within a decade, we can expect that tens of processor cores can be integrated into a single chip which supports hundreds of concurrent threads. However, the scalability of the CMP architecture is highly determined by two important aspects. The first one deals with whether the CMP can efficiently manage the shared platform resources to ensure that all the concurrent threads can make good progress. The second aspect deals with whether the current memory system (on-chip cache and off-chip bandwidth) can support the increasing number of processor cores with the declining share of resource per core. As a graduate student in the Department of Electrical and Computer Engineering at North Carolina State University, I have been working with my advisor, Dr.Yan Solihin, on broad research projects that address these two aspects. In this statement, I will outline my research work and discuss the direction of my future research.